`timescale 1ns/100ps

module SN74HC165_tb();
    reg clk;              // Clock
    reg serial_in;        // Serial Input
    reg shift_load;       // Load
    reg output_enable;    // output Enable
    
    reg [7 : 0] par_in;   // Data Input
    wire serial_out;      // Data Output

    SN74HC165 uu(
        .clk(clk),              // Clock
        .serial_in(serial_in),  // Serial Input
        .shift_load(shift_load),// Load
        .output_enable(output_enable),  // output Enable
    
        .par_in(par_in),        // Data Input
        .serial_out(serial_out) // Data Output
    );
    
    initial begin
        $dumpfile("wave.vcd"); //生成的vcd文件名称
        $dumpvars(0, SN74HC165_tb); //tb模块名称
    end
    
    initial begin
        clk = 0;
        #90
        forever #10 clk = ~clk;
    end

    initial begin
        shift_load = 1;
        serial_in = 0;
        par_in = 8'h53;
        output_enable = 0;
        #10 shift_load = 0;
        #1 shift_load = 1;
        #5 output_enable = 1;
        #400 $stop;
    end
        
    
endmodule



































